Article

Signal processing succession

Article published in New Electronics, 27 May 2003

FPGAs provide significant advantages over conventional signal processing technologies for the defence market.

Before the advent of microprocessors capable of supporting signal processing applications, designs were based on hardware logic. But these solutions were functionally inflexible and generally unable to cope with multiple applications.

This proved problematic for requirement changes during and after development, making products costly to develop and maintain. Furthermore, component obsolescence compromised the longevity of these fixed hardware designs.

Today, many signal processing applications are handled by dsps, but microprocessors still compete where processing flexibility and general program control are required. But a third mature technology provides the same features. FPGAs offer performance and flexibility and can provide significant processing performance and programming advantages.

FPGA signal processing solutions are worth considering in place of complex and less efficient multiprocessor systems. Improvements in time to market, lower development time and lower unit cost also help the defence market with obsolescence management.

Mature, standard development languages and tools provide a solid base for defence type applications and avoid the layers of software that encumber COTS based processor solutions; processing latency can be more easily managed and the product can be brought quickly to market by allowing 'soft development' to start at an early stage.

It is often difficult to identify the optimum technology for a particular application. With few exceptions, fpgas will be faster and/or more cost effective when the signal processing function demands high performance, yet is repetitive and involves minimal branching. In such a case, the hardware created to implement the function will be synthesised efficiently and will operate at high clock rates.

If processing latency needs to be reduced further or functions added, then concurrent operations can be executed if the processing function allows it. In this way, the serial nature of processor based program execution is exceeded by paralleling the instructions. In large designs, this advantage can be significant and performance improvements on this scale can enable alternative solutions such as direct processing at intermediate frequencies (IF) rather than having to down convert to baseband prior to processing.

In more conventional processing tasks - where there is a mixture of pure number crunching, program decision making and control - the traditional choice has been a dsp or processor. However, as long as fpga functionality is being defined with some form of high level language then the same constructs can be defined in the fpga.

And, with a little case - by again using the concurrency inherent in hardware and by calculating all the decision paths simultaneously - the decision making processes can be flattened. Hence, a multistage serial program flow - consisting of comparison, decision and branch - can be flattened into logic that produces the results in a single clock cycle.

In large signal processing systems, where fpga performance has enabled the system to shrink from many processors to a few devices, it may still be wise to allocate a conventional dsp or processor to provide the system control and user I/O.

Skill is required in assessing the appropriate soft and hard function partitioning. If it is judged that sticking with a single technology is more cost effective than a mixture of fpgas and processors, a more efficient solution would be to encapsulate the program flow in an fpga. This can be by direct synthesis of the program flow or by embedding a processor core.

A multitude of languages and programming methods is available. For fpgas, there is a choice of two mature hardware definition languages (hdl) - Vhdl and Verilog - or a range of developing languages, mostly variants of C. These newer languages, while not having the standardisation or maturity of an hdl, can, in some instances, provide productivity benefits. They do not, however, abdicate the need for understanding the hardware function.

In defence applications, the stability, maturity and longevity of Vhdl and Verilog provide significant advantages in the management of obsolescence. However, it is essential that good engineering design practices are used from the outset, firstly - and most significantly - using synchronous design and secondly, conservative design to preserve margins.

Plextek has applied this technique in a defence application that was conceived to be a mixed processor and fpga design. The design included legacy functions, new signal processing tasks, memory, serial monitor and a programmable debug port. The complete functional design was embedded in a single fpga, simplifying pcb design significantly, improving hardware reliability and reducing power consumption. Integration of processor functions into the fpga meant that the number of design teams could be reduced. Furthermore, the use of Vhdl enabled firmware design and simulation to occur concurrently with the hardware development, allowing a pre-production model to be successfully tested after only three months.

It's all in the timing

Asynchronous designs, whether in fpgas or discrete logic, will often present problems, such as timing verification. A synchronous design stands a high chance of operating first time when ported to a new device; even if it does not, debugging is still feasible. By defining the functionality of the signal processing task in an hdl at the highest level of abstraction possible, the function can be ported to a new device in the future with minimal effort.

Obsolete silicon will require replacement with whatever device is appropriate at the time. FPGA performance, pin out and capacity can be almost always guaranteed to exceed that of a previous generation, so migration to the new device in terms of pcb design and function porting is straightforward.

It is common practice with COTS hardware to use general purpose support software and tools. Although this provides a level of obsolescence management, he number of layers of software required to support such an approach can create greater problems than is cures, since the generic nature of these packages tends to decrease their efficiency.

In addition, inclusion of an operating system can further degrade performance. The fpga design benefits from abstraction of the functional design, but the big difference is the compiler that synthesises the hardware is likely to duplicate hardware functions, thereby taking up more silicon real estate, rather than compromising processing speed. If a compiler bloats the object code, this automatically requires more clock cycles to handle the extra instructions serially and, consequently, the processing efficiency diminishes.

HDLs provide various levels of design simulation. Plextek's approach to design is, wherever possible, to use functional simulation based on synchronous rtl prior to synthesis. Post synthesis and post 'place and route' simulation is also possible. In general, simulation tools provide by fpga vendors have sufficiently accurate and detailed information about chip designs to make static path timing analysis a reliable method for timing closure before running the design in the fpga.

Essentially, a processor is limited in what it can do by its serial nature. Of course, code profiling and optimisation are key factors. This may take the form of restructuring code - perhaps in lining to remove branch overheads. It may involve optimisation of key processing functions by converting those modules to assembler. However, the fpga approach to optimisation is more direct. Significant latency reduction can be achieved by restructuring the code and, as long as sufficient fpga resources are available and elements of the processing algorithms can by run in parallel, then latency improvements can be achieved with minimal effort.

In many fpga designs it is also possible to multiply the systems clock and operate internally at higher clock rates. Synthesis tools help to assess the practical operational limits. As with all designs, it is more efficient to achieve the correct design from the start, but it is reassuring that fpgas enable greater freedom in the management of latency.

By Mark Radford